1. Field of the Invention
The present invention relates to a control mode and more specifically relates to a control mode for power converters.
2. Description of Related Art
Various control modes for power converters have been widely used to regulate an output voltage and an output current. Two common control modes for such regulation are voltage-mode and current-mode. Traditional power converters include an error amplifier in the secondary-side circuit of the power converter to sense the output voltage and the output current. The error amplifier provides a feedback signal to a PWM (pulse width modulation) controller in a primary-side circuit via an optical-coupler.
FIG. 1 shows a traditional power converter. Two error amplifiers 78 and 79 are utilized to produce a feedback signal VFB from an output current IO and an output voltage VO. The feedback signal VFB will be provided to a PWM controller 80 in the primary-side circuit of the power converter via an optical-coupler 40. The PWM controller 80 generates a switching signal VPWM to switch a transformer 53 by switching a transistor 20. A switching current IIN flowing through the transistor 20 is converted into a current-sense signal VS via a sense resistor 25(RS). The PWM controller 80 includes a SR flip-flop 81, a first comparator 85, a second comparator 84, a NAND gate 83, and an oscillator 82. The oscillator 82 determines a switching frequency and generates a ramp signal VRMP.
To implement current-mode control, an adder 87 adds up the ramp signal VRMP with the current-sense signal VS to produce a sawtooth signal VSAW. The first comparator 85 compares the feedback signal VFB with the sawtooth signal VSAW to produce the switching signal VPWM. Furthermore, the second comparator 84 compares the current-sense signal VS with a threshold voltage VTH to control the switching signal VPWM and limit the switching current IIN. The switching signal VPWM will regulate the output voltage VO and/or the output current IO.
In order to protect the power converter and meet the safety requirement, it is necessary to limit the maximum of an output power PO and the output current IO. Controlling the power delivered from the primary-side to the secondary-side of the transformer controls the output power PO and the output current IO. The relationship between the output power PO, the output current IO and the switching current IIN of the power converter can be expressed as:PO=VO×IO=η×PIN=η×IIN×VIN  (1)
                              I          IN                =                  [                                    (                                                                    V                    IN                                                        L                    P                                                  ×                                                      T                    ON                    2                                                        2                    ⁢                    T                                                              )                        +                          (                                                I                  A                                ×                                                      T                    ON                                    T                                            )                                ]                                    (        2        )            
Where VO is the output voltage; η is the efficiency; IA is the reflected load current; LP is the primary magnetized inductance; T is the switching period of the switching signal VPWM; and TON is the on-time of the switching signal VPWM.
In order to control the output voltage VO, the on-time TON of the switching signal VPWM is adjusted in response to the feedback signal VFB. When the output current IO increases, the switching current IIN of the transistor 20 will also increase. The switching current IIN of the transistor 20 is converted into the current-sense signal VS. When the current-sense signal VS exceeds a threshold voltage VTH, the on-time TON of the switching signal VPWM will be restricted to limit a maximum input power PIN—MAX. The maximum input power PIN—MAX can be expressed as:
                              P          IN_MAX                =                  [                                    1                              2                ×                T                                      ×                          L              P                        ×                                          (                                                      V                    TH                                                        R                    S                                                  )                            2                                ]                                    (        3        )            The equations (1) and (3) can be rewritten as:
                              I          O                =                                            P              O                                      V              O                                =                                                    η                ×                                  P                  IN_MAX                                                            V                O                                      =                          {                                                η                  ×                                      [                                                                  1                                                  2                          ×                          T                                                                    ×                                              L                        P                                            ×                                                                        (                                                                                    V                              TH                                                                                      R                              S                                                                                )                                                2                                                              ]                                                                    V                  O                                            }                                                          (        4        )            
Since the maximum input power PIN—MAX is limited, the maximum of the output power PO can be limited. Therefore, the output voltage VO will decrease whenever the output current IO increases. However, a propagation delay time TD affects the control for the maximum of the output power PO and the output current IO. If the duration of the propagation delay time TD is too long, the switching signal VPWM will not be able to accurately control the output current IO.
Referring to FIG. 2, a sense resistor 25(RS) converts a switching current IIN into a current-sense signal VS. As shown in FIG. 11, the switching signal VPWM is turned off after the current-sense signal VS exceeds the threshold voltage VTH. The current-sense signal VS exceeds the threshold voltage VTH at the time TONX. However, the switching signal VPWM is not turned off until after a propagation delay time TD. During the propagation delay time TD, the switching current IIN still continues to increase. This will cause an extra switching current IIN-ex to be generated.
The amplitude of this extra switching current IIN-ex is calculated as equation (5) shows. Referring to equations (5) and (6), the extra switching current IIN-ex causes the maximum input power PIN—MAX and output current IO to increase as the input voltage VIN increases.
                              I                      IN            -            ex                          =                  {                                    (                                                                    V                    IN                                                        L                    P                                                  ×                                                      T                    D                                                        2                    ⁢                    T                                                              )                        +                                          [                                                      (                                                                                            V                          IN                                                                          L                          P                                                                    ×                                              T                        ONX                                                              )                                    +                                      I                    A                                                  ]                            ×                                                T                  D                                T                                              }                                    (        5        )                                          P          IN_MAX                =                  [                                    1                              2                ×                T                                      ×                          L              P                        ×                                          (                                                                            V                      TH                                                              R                      S                                                        +                                      I                                          IN                      -                      ex                                                                      )                            2                                ]                                    (        6        )            Therefore, the control precision for limiting the maximum of the output power PO and the output current IO is compromised by the propagation delay time TD of the switching signal VPWM. In recent commercial applications, power converters having smaller size and higher component density become a major trend. Referring to FIG. 1, the optical-coupler 40 and remaining secondary-side control circuitries add significantly to the size and device count of the power converter. This is a serious drawback of this power converter. However, the secondary circuitries are utilized to limit the output current IO. A precise output current IO is particularly required for a power converter with a battery load. Therefore, there exists a need for a primary-side power controller with sufficiently precise constant current limiting.
Ideally, constant current output regulation should limit the amplitude of the output current IO as a constant, at all times. In practice, the current output deviates from the constant output current limit, depending on the output voltage VO and the output current IO. Referring to equation (4), when the output voltage VO decreases, a constant output current IO can be produced by increasing the switching period T and/or reducing the threshold voltage VTH. However, any of several factors can skew the accuracy of this method. Deviation in the primary magnetized inductance LP and a drifting switching frequency (1/T) could also cause the maximum input power PIN—MAX and the output current IO to fluctuate.
Accordingly, the present invention is related to a power-mode control circuitry that can precisely control the maximum output power.
The present invention is also related to a power-mode control circuitry that can precisely regulate the output current in the primary-side circuit of the power converter.